In e.g. a server system, where extremely high reliability is required, memory errors may be a cause for a fatal system fault. For avoiding the problem of memory errors, such a memory having an error correcting function has been developed. This memory is able to detect the presence of a memory error, specify the location where an error has occurred, and to correct the error.
The memory having such error correcting function, or the so-called ECC function, adopts for example a Hamming code as check bits. The number of check bits is correlated with the data bus width, such that, in case the data bus width is N bits, the number of the check bits may be found by taking a log of N with a base of 2 and by adding 2 to the so obtained log. Thus, in a memory having a data bus width of 64 bits, and 256 bits are to be accessed, 8 bits×4=32 error correction bits are needed. For addressing to this problem, the following Patent Document discloses a method for burst transfer of e.g. 64 bits to generate error correction bits in terms of 256 data bits. By this method, 9 error correction bits are sufficient.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-102326